1) Field of the Invention
The present invention relates to a process variation detector and a process variation detecting method that detect a process variation included in an integrated circuit.
2) Description of the Related Art
A semiconductor integrated circuit (hereinafter, simply, “chip”) such as an integrated circuit (IC) and a large scale integration (LSI) is manufactured by repeating many times a process of adding impurities to a silicon wafer and forming an insulation film, a wiring metal film, and the like.
However, when chips are manufactured from a silicon wafer, problems occur that there is a process variation between the manufactured chips and that the chips do not operate normally. Therefore, conventionally, in order to tune the macro circuit within each chip, a tuning circuit is built into each macro circuit by assuming a process variation in advance. At present, a process variation within the chips becomes noticeable along the progress of micro fabrication of a semiconductor device.
After the chips are manufactured, the chips are tested manually, an optimum clock tuning signal is determined, and the determined clock turning signal is input to each macro circuit. With this arrangement, the chips can operate normally even if there is a process variation within the chips.
Japanese Patent Application Lid-Open No. 2003-109379 discloses a technique of generating a timing signal by comparing a potential of a dummy bit line with a reference voltage, thereby improving an operation margin and enabling high-speed operation of the chips.
The conventional technique, however, has problems in that it is not possible to quickly detect a state of a process variation and that each macro circuit included in the chips cannot be tuned efficiently.
Specifically, in specifying a clock tuning signal to be input to a tuning circuit, the chips need to be manufactured and further need to be tested manually. Therefore, this process requires tremendous amounts of time and cost, and places a large load on users who carry out the test.
According to the conventional technique, a common clock tuning signal is used for the same kind of macro circuits. Therefore, a tuning signal cannot be set for each macro circuit of each chip.